Trait SimdBase

pub trait SimdBase:
    'static
    + Sized
    + Clone
    + Copy
    + Sync
    + Send
    + Debug
    + PartialEq
    + Eq
    + Default
    + Pod
    + Zeroable
    + BitXor
    + BitXorAssign
    + BitOr
    + BitOrAssign
    + BitAnd
    + BitAndAssign
    + AddAssign
    + Add<Output = Self>
    + SubAssign
    + Sub<Output = Self>
    + ShlAssign<u64>
    + Shl<u64, Output = Self>
    + ShrAssign<u64>
    + Shr<u64, Output = Self>
    + ShlAssign<Self>
    + Shl<Self, Output = Self>
    + ShrAssign<Self>
    + Shr<Self, Output = Self>
    + ConstantTimeEq
    + ConditionallySelectable
    + AsRef<[Self::Scalar]>
    + AsMut<[Self::Scalar]> {
    type Array: 'static + Sized + Clone + Copy + Sync + Send + Debug + Pod + Zeroable + PartialEq + Eq + Default + Hash + AsRef<[Self::Scalar]> + From<Self> + Into<Self>;
    type Scalar: Scalar;
    type Signed: SimdBase<Scalar = <<Self as SimdBase>::Scalar as Scalar>::Signed> + From<Self> + Into<Self>;
    type Unsigned: SimdBase<Scalar = <<Self as SimdBase>::Scalar as Scalar>::Unsigned> + From<Self> + Into<Self>;
    type BroadcastLoInput: SimdBase<Scalar = Self::Scalar>;

    const LANES: usize;
    const ZERO: Self;

    // Required methods
    fn is_zero(&self) -> bool;
    fn set_lo(value: Self::Scalar) -> Self;
    fn broadcast(value: Self::Scalar) -> Self;
    fn broadcast_lo(of: Self::BroadcastLoInput) -> Self;
    fn extract<const I: usize>(&self) -> Self::Scalar;
    fn shift_left<const BITS: usize>(&self) -> Self;
    fn shift_right<const BITS: usize>(&self) -> Self;
    fn and_not(&self, other: Self) -> Self;
    fn cmp_eq(&self, other: Self) -> Self;
    fn cmp_gt(&self, other: Self) -> Self;
    fn unpack_lo(&self, other: Self) -> Self;
    fn unpack_hi(&self, other: Self) -> Self;
    fn max(&self, other: Self) -> Self;
    fn min(&self, other: Self) -> Self;

    // Provided method
    fn as_array(&self) -> Self::Array { ... }
}

A vector equivalent to [T; Self::Lanes].

Representation

This type should have the same size as [T; Self::Lanes], though it may have increased alignment requirements.

Effects of signedness on shift operations

When Scalar is signed, shift operations are signed shifts. When Scalar is unsigned, shift operations are unsigned shifts.

Example

A signed shift right will add the sign bit

assert_eq!(
    U64x2::from([0xffffffffffffffff, 0x2]) >> 1,
    U64x2::from([0x7fffffffffffffff, 0x1]),
);
assert_eq!(
    // Because the sign bit of 0xffffffffffffffff is 1, shifting right will cause a 1 to be
    // inserted which, in this case, results in the same 0xffffffffffffffff value.
    U64x2::from(I64x2::from(U64x2::from([0xffffffffffffffff, 0x2])) >> 1),
    U64x2::from([0xffffffffffffffff, 0x1]),
);

Required Associated Constants

const LANES: usize

The number of elements of this vector.

const ZERO: Self

A vector where every element is zero.

Required Associated Types

type Array: 'static + Sized + Clone + Copy + Sync + Send + Debug + Pod + Zeroable + PartialEq + Eq + Default + Hash + AsRef<[Self::Scalar]> + From<Self> + Into<Self>

The equivalent array type of this vector.

type Scalar: Scalar

The scalar that this value holds.

type Signed: SimdBase<Scalar = <<Self as SimdBase>::Scalar as Scalar>::Signed> + From<Self> + Into<Self>

The signed version of this vector.

type Unsigned: SimdBase<Scalar = <<Self as SimdBase>::Scalar as Scalar>::Unsigned> + From<Self> + Into<Self>

The unsigned version of this vector.

type BroadcastLoInput: SimdBase<Scalar = Self::Scalar>

A vector of [Self::Scalar; 128 / (8 * std::mem::size_of::<Self::Scalar>())]

Required Methods

fn is_zero(&self) -> bool

Is self == Self::ZERO?

Example

assert!(U32x4::from([0, 0, 0, 0]).is_zero());
assert!(!U32x4::from([1, 0, 0, 0]).is_zero());

fn set_lo(value: Self::Scalar) -> Self

Create a new vector by setting element 0 to value, and the rest of the elements to 0.

Example

assert_eq!(U32x4::from([64, 0, 0, 0]), U32x4::set_lo(64));

fn broadcast(value: Self::Scalar) -> Self

Create a new vector by setting every element to value.

Example

assert_eq!(U32x4::from([64, 64, 64, 64]), U32x4::broadcast(64));

fn broadcast_lo(of: Self::BroadcastLoInput) -> Self

Create a vector by setting every element to element 0 of of.

Example

assert_eq!(U32x4::from([1, 1, 1, 1]), U32x4::broadcast_lo(U32x4::from([1, 2, 3, 4])));

fn extract<const I: usize>(&self) -> Self::Scalar

Get the I-th element of this vector.

Example

let v = U32x4::from([1, 2, 3, 4]);
assert_eq!(v.extract::<0>(), 1);
assert_eq!(v.extract::<1>(), 2);
assert_eq!(v.extract::<2>(), 3);
assert_eq!(v.extract::<3>(), 4);

fn shift_left<const BITS: usize>(&self) -> Self

Shift each element left by BITS.

Example

assert_eq!(U32x4::from([1, 2, 3, 4]).shift_left::<1>(), U32x4::from([2, 4, 6, 8]));

fn shift_right<const BITS: usize>(&self) -> Self

Shift each element right by BITS.

Effects of Signedness

When T is signed, this will shift in sign bits, as opposed to zeroes.

Example

assert_eq!(U32x4::from([1, 2, 3, 4]).shift_right::<1>(), U32x4::from([0, 1, 1, 2]));
assert_eq!(I32x4::from([-1, -2, -3, -4]).shift_right::<1>(), I32x4::from([-1, -1, -2, -2]));

fn and_not(&self, other: Self) -> Self

Compute self & (! other).

Example

assert_eq!(
    U64x2::from([0b11, 0b00]).and_not(U64x2::from([0b10, 0b10])),
    U64x2::from([0b01, 0b00]),
);

fn cmp_eq(&self, other: Self) -> Self

Create a vector where each element is all 1’s if the elements are equal, and all 0’s otherwise.

Example

assert_eq!(
    U64x2::from([1, 2]).cmp_eq(U64x2::from([1, 3])),
    U64x2::from([0xffffffffffffffff, 0]),
);

fn cmp_gt(&self, other: Self) -> Self

Create a vector where each element is all 1’s if the element of self is greater than the corresponding element of other, and all 0’s otherwise.

Example

assert_eq!(
    U64x2::from([1, 28]).cmp_gt(U64x2::from([1, 3])),
    U64x2::from([0, 0xffffffffffffffff]),
);

fn unpack_lo(&self, other: Self) -> Self

Interleave the elements of the low half of self and other.

Example

assert_eq!(
    U32x4::from([101, 102, 103, 104]).unpack_lo(U32x4::from([201, 202, 203, 204])),
    U32x4::from([101, 201, 102, 202]),
);

fn unpack_hi(&self, other: Self) -> Self

Interleave the elements of the high half of self and other.

Example

assert_eq!(
    U32x4::from([101, 102, 103, 104]).unpack_hi(U32x4::from([201, 202, 203, 204])),
    U32x4::from([103, 203, 104, 204]),
);

fn max(&self, other: Self) -> Self

Make a vector consisting of the maximum elements of self and other.

Example

assert_eq!(
    U32x4::from([1, 2, 3, 4]).max(U32x4::from([0, 9, 0, 0])),
    U32x4::from([1, 9, 3, 4]),
);

fn min(&self, other: Self) -> Self

Make a vector consisting of the minimum elements of self and other.

Example

assert_eq!(
    U32x4::from([1, 2, 3, 4]).min(U32x4::from([0, 9, 0, 0])),
    U32x4::from([0, 2, 0, 0]),
);

Provided Methods

fn as_array(&self) -> Self::Array

Convert the vector to an array.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.

Implementors

impl SimdBase for I8x16

const LANES: usize = 16usize

const ZERO: Self

type Scalar = i8

type Array = [i8; 16]

type Signed = I8x16

type Unsigned = U8x16

type BroadcastLoInput = I8x16

impl SimdBase for I8x32

const LANES: usize = 32usize

const ZERO: Self

type Scalar = i8

type Array = [i8; 32]

type Signed = I8x32

type Unsigned = U8x32

type BroadcastLoInput = I8x16

impl SimdBase for I16x8

const LANES: usize = 8usize

const ZERO: Self

type Scalar = i16

type Array = [i16; 8]

type Signed = I16x8

type Unsigned = U16x8

type BroadcastLoInput = I16x8

impl SimdBase for I16x16

const LANES: usize = 16usize

const ZERO: Self

type Scalar = i16

type Array = [i16; 16]

type Signed = I16x16

type Unsigned = U16x16

type BroadcastLoInput = I16x8

impl SimdBase for I32x4

const LANES: usize = 4usize

const ZERO: Self

type Scalar = i32

type Array = [i32; 4]

type Signed = I32x4

type Unsigned = U32x4

type BroadcastLoInput = I32x4

impl SimdBase for I32x8

const LANES: usize = 8usize

const ZERO: Self

type Scalar = i32

type Array = [i32; 8]

type Signed = I32x8

type Unsigned = U32x8

type BroadcastLoInput = I32x4

impl SimdBase for I64x2

const LANES: usize = 2usize

const ZERO: Self

type Scalar = i64

type Array = [i64; 2]

type Signed = I64x2

type Unsigned = U64x2

type BroadcastLoInput = I64x2

impl SimdBase for I64x4

const LANES: usize = 4usize

const ZERO: Self

type Scalar = i64

type Array = [i64; 4]

type Signed = I64x4

type Unsigned = U64x4

type BroadcastLoInput = I64x2

impl SimdBase for U8x16

const LANES: usize = 16usize

const ZERO: Self

type Scalar = u8

type Array = [u8; 16]

type Signed = I8x16

type Unsigned = U8x16

type BroadcastLoInput = U8x16

impl SimdBase for U8x32

const LANES: usize = 32usize

const ZERO: Self

type Scalar = u8

type Array = [u8; 32]

type Signed = I8x32

type Unsigned = U8x32

type BroadcastLoInput = U8x16

impl SimdBase for U16x8

const LANES: usize = 8usize

const ZERO: Self

type Scalar = u16

type Array = [u16; 8]

type Signed = I16x8

type Unsigned = U16x8

type BroadcastLoInput = U16x8

impl SimdBase for U16x16

const LANES: usize = 16usize

const ZERO: Self

type Scalar = u16

type Array = [u16; 16]

type Signed = I16x16

type Unsigned = U16x16

type BroadcastLoInput = U16x8

impl SimdBase for U32x4

const LANES: usize = 4usize

const ZERO: Self

type Scalar = u32

type Array = [u32; 4]

type Signed = I32x4

type Unsigned = U32x4

type BroadcastLoInput = U32x4

impl SimdBase for U32x8

const LANES: usize = 8usize

const ZERO: Self

type Scalar = u32

type Array = [u32; 8]

type Signed = I32x8

type Unsigned = U32x8

type BroadcastLoInput = U32x4

impl SimdBase for U64x2

const LANES: usize = 2usize

const ZERO: Self

type Scalar = u64

type Array = [u64; 2]

type Signed = I64x2

type Unsigned = U64x2

type BroadcastLoInput = U64x2

impl SimdBase for U64x4

const LANES: usize = 4usize

const ZERO: Self

type Scalar = u64

type Array = [u64; 4]

type Signed = I64x4

type Unsigned = U64x4

type BroadcastLoInput = U64x2